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MC100EP16VC 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
Description
The EP16VC is a differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output. The EP16VC provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and QHG outputs. When the EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and EN goes HIGH, it will force the QHG LOW and the QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and QHG outputs remain in their disabled state as long as the EN input is held HIGH. The EN input has no influence on the Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output. The VBB/D pin is internally dedicated and available for differential interconnect. VBB/D may rebias AC coupled inputs. When used, decouple VBB/D and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 1.5 mA. When not used, VBB/D should be left open. The 100 Series contains temperature compensation.
Features
http://onsemi.com MARKING DIAGRAMS*
8 8 1 SOIC-8 D SUFFIX CASE 751 KEP66 ALYW G
1 8
8 1
TSSOP-8 DT SUFFIX CASE 948R 1
KP66 ALYWG G
DFN8 MN SUFFIX CASE 506AA
1 A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
* 310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
* Gain > 200 * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * * * * *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State QHG Output Will Default LOW with D Inputs Open or at VEE VBB Output Pb-Free Packages are Available
(c) Semiconductor Components Industries, LLC, 2006
December, 2006 - Rev. 5
1
Publication Order Number: MC10EP16VC/D
3G MG G 4
MC100EP16VC
Table 1. PIN DESCRIPTION
Q 1 8 VCC D* Q D 2 7 QHG QHG, QHG EN* VBB/D VBB/D 3 LEN VBB EN 4 Q OE 6 QHG VCC VEE EP 5 VEE Pin ECL Data Input ECL Data Output ECL High Gain Data Outputs ECL Enable Input Reference Voltage Output / ECL Data Input Positive Supply Negative Supply Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Function
LATCH D
*Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Level 1 Level 1 Value 75 kW N/A > 4 kV > 200 V > 2 kV Pb-Free Pkg Level 1 Level 3 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC-8 TSSOP-8 DFN8 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 167 Devices
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Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC qJA Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP DFN8 DFN8 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 1.5 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 129 84 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current D 0.5 Min 25 2125 1305 2075 1355 1730 2.0 1845 Typ 36 2250 1400 Max 45 2375 1555 2420 1675 1960 3.3 150 0.5 Min 30 2125 1305 2075 1355 1730 2.0 1845 25C Typ 40 2250 1400 Max 50 2375 1555 2420 1675 1960 3.3 150 0.5 Min 32 2125 1305 2075 1355 1730 2.0 1845 85C Typ 42 2250 1400 Max 52 2375 1555 2420 1675 1960 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP16VC
Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current D 0.5 Min 25 3825 3005 3775 3055 3430 2.0 3545 Typ 36 3950 3100 Max 45 4075 3255 4120 3375 3660 5.0 150 0.5 Min 30 3825 3005 3775 3055 3430 2.0 3545 25C Typ 40 3950 3100 Max 50 4075 3255 4120 3375 3660 5.0 150 0.5 Min 32 3825 3005 3775 3055 3430 2.0 3545 85C Typ 42 3950 3100 Max 52 4075 3255 4120 3375 3660 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. All loading with 50 W to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 8)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Input HIGH Current Input LOW Current 0.5 Min 25 -1175 -1995 -1225 -1945 -1570 -1455 VEE + 2.0 Typ 36 -1050 -1900 Max 45 -925 -1745 -880 -1625 -1340 0.0 Min 30 -1175 -1995 -1225 -1945 -1570 -1455 VEE + 2.0 25C Typ 40 -1050 -1900 Max 50 -925 -1745 -880 -1625 -1340 0.0 Min 32 -1175 -1995 -1225 -1945 -1570 -1455 VEE + 2.0 85C Typ 42 -1050 -1900 Max 52 -925 -1745 -880 -1625 -1340 0.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 11)
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (Figure 2) Propagation Delay (Differential) Q (Differential) QHG, QHG (Single-Ended) Q (Single-Ended) QHG, QHG Setup Time Hold Time Duty Cycle Skew (Note 12) RMS Random Clock Jitter (Figure 2) Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% - 80%) HG Q Q QHG, QHG 25 150 200 70 EN = L to D EN =H to D EN = L to D EN =H to D 200 250 250 300 50 100 100 50 Min Typ >3 280 360 330 410 15 60 50 15 5.0 0.2 800 800 300 130 20 <1 1200 1200 400 220 25 150 250 80 350 450 400 500 250 300 300 350 50 100 100 50 Max Min 25C Typ >3 310 380 360 430 5 40 40 20 5.0 0.2 800 800 350 150 20 <1 1200 1200 450 240 25 150 250 100 400 500 450 550 275 325 325 375 50 100 100 50 Max Min 85C Typ >3 340 430 390 480 18 10 5 20 5.0 0.2 800 800 350 170 20 <1 1200 1200 500 270 425 525 475 575 Max Unit GHz ps
tS tH tSKEW tJITTER VPP tr tf
ps ps ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 12. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS)
E EEEE E E E E E E E E E E E E E E E EEEE E E E E E E E E E E E E E E EEEEEE EEEEEE EE
0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz)
Figure 2. Fmax/Jitter for QHG, QHG Output
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MC100EP16VC
900 800 VOUTpp (mV) 700 600 500 400 9 8 7 6 5 4 3 2 1 4000 JITTEROUT ps (RMS) JITTEROUT ps (RMS)
200 100 0
0
500
1000
1500
2000
2500
3000
3500
FREQUENCY (MHz)
Figure 3. Fmax/Jitter for Q Output
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0
9 8 7 6 5 4 3 2 1
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 4. Fmax/Jitter for QHG, QHG Output
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EE EE EE EE
EEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEE
E E E E E E E E EEEEEEEEE E E E E E E E E EEEEEEEEE EEEEEEE EEEEEEE
300
MC100EP16VC
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS)
Driver Device Q Zo = 50 W 50 W 50 W D
Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
E EEEEE EEEEEEEEEEEEE E EEEEE EEEEEEEEEEEEE EEEEEEE EEEEEEE
0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
Figure 5. Fmax/Jitter for Q Output
Q
Zo = 50 W
D Receiver Device
VTT VTT = VCC - 2.0 V
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MC100EP16VC
ORDERING INFORMATION
Device MC100EP16VCD MC100EP16VCDG MC100EP16VCDR2 MC100EP16VCDR2G MC100EP16VCDT MC100EP16VCDTG MC100EP16VCDTR2 MC100EP16VCDTR2G MC100EP16VCMNR4 MC100EP16VCMNR4G Package SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) DFN8 DFN8 (Pb-Free) Shipping 98 Units / Rail 98 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 100 Units / Rail 100 Units / Rail 2500 / Rail 2500 / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EP16VC
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X-
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC100EP16VC
PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8 1
5
L
PIN 1 IDENT
4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
G DETAIL E
-W-
DIM A B C D F G K L M
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MC100EP16VC
PACKAGE DIMENSIONS
DFN8 CASE 506AA-01 ISSUE D
1
D
A B
PIN ONE REFERENCE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 --- 0.25 0.35
2X
0.10 C
2X
0.10 C
0.10 C
8X
0.08 C
SEATING PLANE
A1
e/2
1 8X 4
L
K
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
CCC CCC CCC CCC
8
E
TOP VIEW
A (A3) C e
SIDE VIEW D2
E2
5 8X
b
0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
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MC100EP16VC/D

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